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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
I 2 C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Notes 14, 15, Figure 4)
(DV DD = +2.7V to +5.25V, AV DD = +4.75V to +5.25V, V DGND = V AGND = 0, external V REFADC = +2.5V, external V REFDAC = +2.5V,
C REF = 0.1μF, T A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
C B = 100pF max
MIN MAX
C B = 400pF
MIN MAX
UNITS
Serial Clock Frequency
Setup Time (Repeated) START
Condition
Hold Time (Repeated) START
Condition
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
f SCL
t SU:STA
t HD:STA
t LOW
t HIGH
t SU:DAT
0
160
160
160
80
10
3.4
0
160
160
320
120
10
1.7
MHz
ns
ns
ns
ns
ns
Data Hold Time
SCL Rise Time
t HD:DAT
t RCL
(Note 17)
4
10
70
40
4
20
150
80
ns
ns
After a repeated START
SCL Rise Time
t RCL1
condition and after an
10
80
20
160
ns
acknowledge bit
SCL Fall Time
SDA Rise Time
SDA Fall Time
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
t FCL
t RDA
t FDA
t SU:STO
C B
(Note 20)
10
10
10
160
40
80
80
100
20
20
20
160
80
160
160
400
ns
ns
ns
ns
ns
Pulse Width of Spikes Suppressed
by the Input Filter
t SP
(Note 21)
0
10
0
10
ns
MISCELLANEOUS TIMING CHARACTERISTICS (Note 15)
(DV DD = +2.7V to +5.25V, AV DD = +4.75V to +5.25V, V DGND = V AGND = 0, external V REFADC = +2.5V, external V REFDAC = +2.5V,
C REF = 0.1μF, T A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Time to Wait After a Write
Command Before Reading Back
t RDBK
(Note 22)
1
μs
Data from the Same Location
CNVST Active-Low Pulse Width in
ADC Clock Mode 01
t CNV01
20
ns
CNVST Active-Low Pulse Width in
ADC Clock Mode 11 to Initiate a
t CNV11
20
ns
Temperature Conversion
CNVST Active-Low Pulse Width in
ADC Clock Mode 11 for ADCIN1/2
t ACQ11A
1.5
μs
Acquisition
ADC Power-Up Time (External
Reference)
ADC Power-Up Time (Internal
Reference)
t APUEXT
t APUINT
1.1
70
μs
μs
_______________________________________________________________________________________
7
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